BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Denver
X-LIC-LOCATION:America/Denver
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260422T000713Z
LOCATION:405-406-407
DTSTART;TZID=America/Denver:20231117T093000
DTEND;TZID=America/Denver:20231117T100000
UID:submissions.supercomputing.org_SC23_sess462_ws_hmem102@linklings.com
SUMMARY:Persistent Snapshot Isolation with Unlimited Reads on Commodity Ha
 rdware Transactional Memory
DESCRIPTION:Miguel Figueiredo and Daniel Castro (INESC-ID, Instituto Super
 ior Técnico, Universidade de Lisboa); Alexandro Baldassin (São Paulo State
  University (Unesp)); and João Barreto and Paolo Romano (INESC-ID, Institu
 to Superior Técnico, Universidade de Lisboa)\n\nPersistent Memory (PM) has
  been proposed and commercially used as a novel generation of storage devi
 ces capable of competing with both primary and secondary memory, attaining
  features such as data persistency and byte addressability.\n\nThese devic
 es paved the way for researchers to develop Transactional Memories (TMs) t
 hat, besides providing atomic transactions in main memory, because this me
 mory can also be persistent, also deliver durable transactions. Unfortunat
 ely, combining PM and TM is challenging, as the most efficient implementat
 ions of TM, i.e., Hardware Transaction Memories (HTMs), operate at the lev
 el of volatile CPU caches.\n\nWe present our early-stage work on PSI, the 
 first durable Persistent Hardware Transaction Memory for IBM's POWER syste
 ms. Our work builds on SI-HTM, which is a volatile HTM solution, and expan
 ds it with durability. We show that PSI imposes a relatively low overhead 
 of 23% when compared with a volatile solution.\n\nTag: Data Movement and M
 emory, Fault Handling and Tolerance, Hardware Technologies, Heterogeneous 
 Computing, I/O and File Systems, Performance Measurement, Modeling, and To
 ols, Programming Frameworks and System Software, Security\n\nRegistration 
 Category: Workshop Reg Pass\n\nSession Chairs: João Barreto (INESC-ID, IST
 , University of Lisbon; Universidade de Lisboa); Hatem ElShazly (Sony); An
 tonio J. Peña (Barcelona Supercomputing Center (BSC); Universitat Politècn
 ica de Catalunya (UPC), Spain); and Harald Servat (Intel Corporation)\n\n
END:VEVENT
END:VCALENDAR