BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Denver
X-LIC-LOCATION:America/Denver
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260422T000610Z
LOCATION:403-404
DTSTART;TZID=America/Denver:20231117T083000
DTEND;TZID=America/Denver:20231117T120000
UID:submissions.supercomputing.org_SC23_sess459@linklings.com
SUMMARY:Ninth International Workshop on Heterogeneous High-Performance Rec
 onfigurable Computing (H2RC 2023)
DESCRIPTION:Stencil-HMLS:  A Multi-Layered Approach to the Automatic Optim
 ization of Stencil Codes on FPGA\n\nThe challenges associated with effecti
 vely programming FPGAs have been a major blocker in popularizing reconfigu
 rable architectures for HPC workloads. However new compiler technologies, 
 such as MLIR, are providing new capabilities which potentially deliver the
  ability to extract domain specific info...\n\n\nGabriel Rodriguez-Canal, 
 Nick Brown, and Maurice Jamieson (University of Edinburgh, Edinburgh Paral
 lel Computing Centre (EPCC)) and Emilien Bauer, Anton Lydike, and Tobias G
 rosser (University of Edinburgh)\n---------------------\nClosing Remarks\n
 ---------------------\nEnabling Communication with FPGA-Based Network-Atta
 ched Accelerators for HPC Workloads\n\nThe use of stand-alone, network-cou
 pled FPGA accelerators is intended to significantly increase the energy ef
 ficiency of HPC applications and thus also of HPC data centers. A loose co
 upling between the nodes of the HPC data center and the FPGAs is establish
 ed through the high-speed network of the da...\n\n\nSteffen Christgau and 
 Dylan Everingham (Zuse Institute Berlin); Florian Mikolajczak (University 
 of Potsdam); Niklas Schelten (Fraunhofer Heinrich Hertz Institute); Bettin
 a Schnor and Max Schroetter (University of Potsdam); and Benno Stabernack 
 and Fritjof Steinert (Fraunhofer Heinrich Hertz Institute, University of P
 otsdam)\n---------------------\nChameleon:  A Disaggregated CPU, GPU, and 
 FPGA System for Retrieval-Augmented Language Models\n\nA Retrieval-Augment
 ed Language Model (RALM) augments a generative language model by retrievin
 g context-specific knowledge from an external database via vector search. 
 This strategy facilitates impressive text generation quality even with sma
 ller models, thus saving orders of magnitude of computation...\n\n\nWenqi 
 Jiang and Gustavo Alonso (ETH Zurich - Swiss Federal Institute of Technolo
 gy)\n---------------------\nInvited Talk: Spatial Computing with AMD AI En
 gines\n\nNew compute architectures with high performance cores, distribute
 d memories and hardware accelerated data movement are becoming available i
 n new form factors, even finding their ways into laptops.  In this talk, I
  will discuss one such architecture, AMD’s AI Engine, and show how researc
 hers ar...\n\n\nPhil James-Roxby (AMD Research)\n---------------------\nAl
 tis-SYCL:  Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs a
 nd FPGAs\n\nIn this work, we introduce Altis-SYCL, a benchmark suite based
  on SYCL for GPUs and FPGAs. For developing Altis-SYCL, we leverage the on
 eAPI heterogeneous programming framework in two consecutive steps: 1) by u
 sing the modern Altis GPGPU benchmark suite as baseline and migrating it f
 rom CUDA to SYCL...\n\n\nChristoph Weckert, Leonardo Solis-Vasquez, Julian
  Oppermann, and Andreas Koch (Technical University of Darmstadt) and Olive
 r Sinnen (University of Auckland)\n---------------------\nOctoRay: Framewo
 rk for Scalable FPGA Cluster Acceleration of Python Big Data Applications\
 n\nWe introduce OctoRay, a Python framework which allows users to easily c
 ombine several FPGA and Python libraries to run their big data analytics p
 ipelines in parallel on FPGA-enabled clusters. We show that OctoRay provid
 es users with multiple levels of freedom, regarding the type of FPGA, the 
 choice ...\n\n\nZaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Die
 rick, and H. Peter Hofstee (Delft University of Technology)\n-------------
 --------\nH2RC'23 – Morning Break\n---------------------\nTydi-lang:  A La
 nguage for Typed Streaming Hardware\n\nTransferring composite data structu
 res with variable-length fields often requires designing unique protocols,
  causing incompatibility issues and decreased collaboration among hardware
  developers, especially in the open-source community. Because the high-lev
 el meaning of a protocol is often lost in t...\n\n\nYongding Tian, Matthij
 s Reukers, and Zaid Al-Ars (Delft University of Technology); Peter Hofstee
  (Delft University of Technology, IBM Infrastructure Austin); and Matthijs
  Brobbel, Johan Peltenburg, and Jeroen Straten (Voltron Data)\n-----------
 ----------\nOpening Remarks\n\nTag: Architecture and Networks\n\nRegistrat
 ion Category: Workshop Reg Pass\n\nSession Chairs: Jason Bakos (University
  of South Carolina); Franck Cappello (Argonne National Laboratory (ANL), U
 niversity of Illinois); Torsten Hoefler (ETH Zürich, Microsoft Corporation
 ); Kenneth O'Brien (Advanced Micro Devices, Inc. (AMD)); and Christian Ple
 ssl (Paderborn University, Germany)
END:VEVENT
END:VCALENDAR
