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DTSTART;TZID=America/Denver:20231113T170600
DTEND;TZID=America/Denver:20231113T173000
UID:submissions.supercomputing.org_SC23_sess457_ws_mlg101@linklings.com
SUMMARY:An Analysis of Graph Neural Network Memory Access Patterns
DESCRIPTION:Satoshi Iwata (University of Wisconsin, Fujitsu Ltd); Remzi H.
  Arpaci-Dusseau (University of Wisconsin); and Akihiko Kasagi (Fujitsu Ltd
 )\n\nGraph Neural Networks (GNNs) are becoming increasingly popular for ap
 plying neural networks to graph data. However, as the size of the input gr
 aph increases, the GPU memory wall problem becomes an important issue. Sin
 ce both current solutions to reduce the memory footprint, such as mini-bat
 ch approaches and the use of memory-efficient tensor manipulations, have d
 rawbacks, we attempt to solve the problem by expanding the memory size usi
 ng a virtual memory technology. To overcome the data transfer overhead of 
 virtual memory technology, in this paper we focus on analyzing the memory 
 access pattern of GNNs with the goal of reducing the data transfer latency
  perceived by the user. A preliminary result of applying optimization tech
 niques guided by our analysis results shows a 40% reduction in the executi
 on time of a combination of training and testing.\n\nTag: Artificial Intel
 ligence/Machine Learning, Graph Algorithms and Frameworks\n\nRegistration 
 Category: Workshop Reg Pass\n\nSession Chairs: Seung-Hwan Lim (Oak Ridge N
 ational Laboratory (ORNL)); José Moreira (IBM); Catherine Schuman (Univers
 ity of Tennessee, Knoxville); and Richard Vuduc (Georgia Institute of Tech
 nology)\n\n
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