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DTSTAMP:20260422T000711Z
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DTSTART;TZID=America/Denver:20231113T161000
DTEND;TZID=America/Denver:20231113T163000
UID:submissions.supercomputing.org_SC23_sess455_ws_risc111@linklings.com
SUMMARY:Is RISC-V Ready for HPC Prime-Time:  Evaluating the 64-Core Sophon
  SG2042 RISC-V CPU
DESCRIPTION:Nick Brown (Edinburgh Parallel Computing Centre (EPCC), Univer
 sity of Edinburgh) and Maurice Jamieson and Joseph Lee (Edinburgh Parallel
  Computing Centre (EPCC))\n\nThe Sophon SG2042 is the world's first commod
 ity 64-core RISC-V CPU for high performance workloads and an important que
 stion is whether the SG2042 has the potential to encourage the HPC communi
 ty to embrace RISC-V.\n\nWe undertake a performance exploration of the SG2
 042 against existing RISC-V hardware and high performance x86 CPUs in use 
 by modern supercomputers. Leveraging the RAJAPerf benchmarking suite, we d
 iscover that on average, the SG2042 delivers, per core, between five and t
 en times the performance compared to the nearest widely available RISC-V h
 ardware. We found that, on average, the x86 high performance CPUs under te
 st outperform the SG2042 by between four and eight times for multi-threade
 d workloads, although some individual kernels do perform faster on the SG2
 042. The result of this work is a performance study that not only contrast
 s this new RISC-V CPU against existing technologies, but furthermore share
 s performance best practice.\n\nTag: Architecture and Networks, Hardware T
 echnologies\n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs:
  Nick Brown (Edinburgh Parallel Computing Centre (EPCC); University of Edi
 nburgh, Scotland); John Davis (Openchip); Andy Gothard (Siemens); John Lei
 del (Tactical Computing Laboratories LLC, Texas Tech University); and Mich
 ael Wong (Codeplay Software Ltd, Khronos Group Inc)\n\n
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