BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Denver
X-LIC-LOCATION:America/Denver
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260422T000712Z
LOCATION:507
DTSTART;TZID=America/Denver:20231113T153000
DTEND;TZID=America/Denver:20231113T155000
UID:submissions.supercomputing.org_SC23_sess455_ws_risc109@linklings.com
SUMMARY:An Empirical Comparison of the RISC-V and AArch64 Instruction Sets
DESCRIPTION:Daniel Weaver and Simon McIntosh-Smith (University of Bristol)
 \n\nIn this work we perform one of the first in-depth, empirical compariso
 ns of the Arm and RISC-V instruction sets. We compare a series of benchmar
 ks compiled with GCC 9.2 and 12.2, targeting the scalar subsets of Arm's A
 rmv-8a and RISC-V's rv64g. We analyze instruction counts, critical paths a
 nd windowed critical paths to get an estimate of performance differences b
 etween the two instruction sets, determining where each has advantages and
  disadvantages. The results show the instruction sets are relatively close
 ly matched on the metrics we evaluated for the benchmarks we considered, i
 ndicating that neither ISA has a large, inherent advantage over the other,
  architecturally.\n\nTag: Architecture and Networks, Hardware Technologies
 \n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Nick Brown
  (Edinburgh Parallel Computing Centre (EPCC); University of Edinburgh, Sco
 tland); John Davis (Openchip); Andy Gothard (Siemens); John Leidel (Tactic
 al Computing Laboratories LLC, Texas Tech University); and Michael Wong (C
 odeplay Software Ltd, Khronos Group Inc)\n\n
END:VEVENT
END:VCALENDAR
