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DTSTART;TZID=America/Denver:20231113T171000
DTEND;TZID=America/Denver:20231113T173000
UID:submissions.supercomputing.org_SC23_sess455_ws_risc105@linklings.com
SUMMARY:Challenges and Opportunities in the Co-Design of Convolutions and 
 RISC-V Vector Processors
DESCRIPTION:Sonia Rani Gupta, Nikela Papadopoulou, and Miquel Pericàs (Cha
 lmers University of Technology, Sweden)\n\nThe RISC-V "V" extension introd
 uces vector processing to the RISC-V architecture. Unlike most SIMD extens
 ions, it supports long vectors which can result in significant improvement
  of multiple applications. We present our ongoing research to implement an
 d optimize a vectorized Winograd algorithm used in convolutional layers on
  RISC-V Vector(RISC-VV) processors. Our study identifies effective techniq
 ues for optimizing the kernels of Winograd on RISC-VV using intrinsic inst
 ructions, and showcases how certain instructions offer better performance.
  Our co-design findings suggest that the Winograd algorithm benefits from 
 vector lengths up to 2048 bits and cache sizes up to 64MB.\n\nWe use our e
 xperience with Winograd to highlight potential enhancements for the standa
 rd that would simplify code generation and aid low-level programming. Fina
 lly, we share our experience from experimenting with forks of gem5 for RIS
 C-VV and stress the importance of a mature software ecosystem, to facilita
 te design space exploration and architectural optimization.\n\nTag: Archit
 ecture and Networks, Hardware Technologies\n\nRegistration Category: Works
 hop Reg Pass\n\nSession Chairs: Nick Brown (Edinburgh Parallel Computing C
 entre (EPCC); University of Edinburgh, Scotland); John Davis (Openchip); A
 ndy Gothard (Siemens); John Leidel (Tactical Computing Laboratories LLC, T
 exas Tech University); and Michael Wong (Codeplay Software Ltd, Khronos Gr
 oup Inc)\n\n
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