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DTSTART;TZID=America/Denver:20231113T163000
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UID:submissions.supercomputing.org_SC23_sess455_ws_risc103@linklings.com
SUMMARY:Short Reasons for Long Vectors in HPC CPUs:  A Study Based on RISC
 -V
DESCRIPTION:Pablo Vizcaino (Barcelona Supercomputing Center (BSC)); Georgi
 os Leronymakis, Nikolaos Dimou, and Vassilis Papaefstathiou (Foundation fo
 r Research and Technology - Hellas (FORTH), Greece); and Jesus Labarta and
  Filippo Mantovani (Barcelona Supercomputing Center (BSC))\n\nFor years, S
 IMD/vector units have enhanced the capabilities of modern CPUs in High-Per
 formance Computing (HPC) and mobile technology. Typical commercially-avail
 able SIMD units process up to 8 double-precision elements with one instruc
 tion. The optimal vector width and its impact on CPU throughput due to mem
 ory latency and bandwidth remain challenging research areas. This study ex
 amines the behavior of four computational kernels on a RISC-V core connect
 ed to a customizable vector unit, capable of operating up to 256 double pr
 ecision elements per instruction. The four codes have been purposefully se
 lected to represent non-dense workloads: SpMV, BFS, PageRank, FFT. The exp
 erimental setup allows us to measure their performance while varying the v
 ector length, the memory latency, and bandwidth. Our results not only show
  that larger vector lengths allow for better tolerance of limitations in t
 he memory subsystem but also offer hope to code developers beyond dense li
 near algebra.\n\nTag: Architecture and Networks, Hardware Technologies\n\n
 Registration Category: Workshop Reg Pass\n\nSession Chairs: Nick Brown (Ed
 inburgh Parallel Computing Centre (EPCC); University of Edinburgh, Scotlan
 d); John Davis (Openchip); Andy Gothard (Siemens); John Leidel (Tactical C
 omputing Laboratories LLC, Texas Tech University); and Michael Wong (Codep
 lay Software Ltd, Khronos Group Inc)\n\n
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