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UID:submissions.supercomputing.org_SC23_sess455@linklings.com
SUMMARY:Second International Workshop on RISC-V for HPC
DESCRIPTION:Short Reasons for Long Vectors in HPC CPUs:  A Study Based on 
 RISC-V\n\nFor years, SIMD/vector units have enhanced the capabilities of m
 odern CPUs in High-Performance Computing (HPC) and mobile technology. Typi
 cal commercially-available SIMD units process up to 8 double-precision ele
 ments with one instruction. The optimal vector width and its impact on CPU
  throughput du...\n\n\nPablo Vizcaino (Barcelona Supercomputing Center (BS
 C)); Georgios Leronymakis, Nikolaos Dimou, and Vassilis Papaefstathiou (Fo
 undation for Research and Technology - Hellas (FORTH), Greece); and Jesus 
 Labarta and Filippo Mantovani (Barcelona Supercomputing Center (BSC))\n---
 ------------------\nAn Empirical Comparison of the RISC-V and AArch64 Inst
 ruction Sets\n\nIn this work we perform one of the first in-depth, empiric
 al comparisons of the Arm and RISC-V instruction sets. We compare a series
  of benchmarks compiled with GCC 9.2 and 12.2, targeting the scalar subset
 s of Arm's Armv-8a and RISC-V's rv64g. We analyze instruction counts, crit
 ical paths and windo...\n\n\nDaniel Weaver and Simon McIntosh-Smith (Unive
 rsity of Bristol)\n---------------------\nIs RISC-V Ready for HPC Prime-Ti
 me:  Evaluating the 64-Core Sophon SG2042 RISC-V CPU\n\nThe Sophon SG2042 
 is the world's first commodity 64-core RISC-V CPU for high performance wor
 kloads and an important question is whether the SG2042 has the potential t
 o encourage the HPC community to embrace RISC-V.\n\nWe undertake a perform
 ance exploration of the SG2042 against existing RISC-V hardwar...\n\n\nNic
 k Brown (Edinburgh Parallel Computing Centre (EPCC), University of Edinbur
 gh) and Maurice Jamieson and Joseph Lee (Edinburgh Parallel Computing Cent
 re (EPCC))\n---------------------\nLightning Vendor Talk:  The InspireSemi
  Next Gen Thunderbird Compute Accelerator for HPC, AI, and Graph Analytics
 \n\nDoug will give an overview of Austin-based InspireSemi’s disruptive ne
 xt generation Thunderbird compute accelerator targeting HPC and graph anal
 ytics applications. This RISC-V based “supercomputer-cluster-on-a-chip” pa
 cks 1,536 high performance CPU cores (all FP64 double-precision ...\n\n\nD
 oug Norton\n---------------------\nLightning Vendor Talk:  E4 Experience w
 ith RISC-V in HPC\n\nMonte Cimone is a fully-operational multi-blade compu
 ter prototype and hardware-software test-bed based upon E4's RV007 blade s
 ystem which comprises of the SiFive Freedom U740 SoC, which is a double-pr
 ecision capable multi-core, 64-bit RISC-V CPU. In this talk, I will provid
 e an overview of the curr...\n\n\nDaniele Gregori\n---------------------\n
 RISC-V for HPC – Afternoon Break\n---------------------\nLightning Vendor 
 Talk:  SG2042 Empowering RISC-V in High-Performance Computing\n\nSophgo in
 troduced the industry's first server-grade RISC-V CPU, the SG2042, which i
 s helping RISC-V make strides in the high-performance computing arena. Wit
 h a 9-12 stage pipeline design, out-of-order execution support, and a cloc
 k speed of up to 2GHz, the SG2042 features 16 clusters, each with a m...\n
 \n\nLiuxi Yang\n---------------------\nAutomatic Generation of Micro-Kerne
 ls for Performance Portability of Matrix Multiplication on RISC-V Vector P
 rocessors\n\nIn this paper, we propose and evaluate several optimized impl
 ementations of the general matrix multiplication (Gemm) on two different R
 ISC-V architecture cores implementing the RISC-V vector extension (RVV): C
 906 and C910 from T-HEAD. Specifically, we address the performance portabi
 lity problem acro...\n\n\nFrancisco Igual and Luis Piñuel (Complutense Uni
 versity of Madrid); Sandra Catalán (Jaume I University, Spain); Héctor Mar
 tínez (Universidad de Córdoba); and Adrián Castelló and Enrique Quintana-O
 rtí (Universidad Politecnica de Valencia)\n---------------------\nRISC-V E
 verywhere\n\nThis talk will include information about Open Standards, who 
 is using RISC-V for HPC, how we get to application and system software por
 tability, what we've done this year and what is coming up. It is a basic i
 ntroduction and should help people considering RISC-V prepare to take next
  steps in creatin...\n\n\nMark Himelstein (RISC-V International)\n--------
 -------------\nEvaluating HPX and Kokkos on RISC-V Using an Astrophysics A
 pplication Octo-Tiger\n\nIn recent years, computers based on the RISC-V ar
 chitecture have raised broad interest in the high-performance computing (H
 PC) community. As the RISC-V community develops the core instruction set a
 rchitecture (ISA) along with ISA extensions, the HPC community has been ac
 tively ensuring HPC applicati...\n\n\nPatrick Diehl, Gregor Daiss, Steven 
 Brandt, Alireza Kheirkhahan, and Hartmut Kaiser (Louisiana State Universit
 y) and Christopher Taylor and John Leidel (Tactical Computing Laboratories
 )\n---------------------\nChallenges and Opportunities in the Co-Design of
  Convolutions and RISC-V Vector Processors\n\nThe RISC-V "V" extension int
 roduces vector processing to the RISC-V architecture. Unlike most SIMD ext
 ensions, it supports long vectors which can result in significant improvem
 ent of multiple applications. We present our ongoing research to implement
  and optimize a vectorized Winograd algorithm used...\n\n\nSonia Rani Gupt
 a, Nikela Papadopoulou, and Miquel Pericàs (Chalmers University of Technol
 ogy, Sweden)\n---------------------\nIntroduction and Welcome\n\nNick Brow
 n (Edinburgh Parallel Computing Centre (EPCC))\n---------------------\nSec
 ond International Workshop on RISC-V for HPC\n\nRISC-V is an open standard
  Instruction Set Architecture (ISA) which enables the open development of 
 CPUs and a shared common software ecosystem. There are already approximate
 ly 10 billion RISC-V cores, which is expected to accelerate rapidly. Nonet
 heless, for all the successes that RISC-V has faced,...\n\n\nNick Brown (E
 dinburgh Parallel Computing Centre (EPCC), University of Edinburgh); John 
 Davis (Barcelona Supercomputing Center (BSC)); John Leidel (Tactical Compu
 ting Laboratories, Texas Advanced Computing Center (TACC)); Michael Wong (
 Codeplay Software Ltd, UK); and Andy Gothard (Siemens)\n------------------
 ---\nLightning Vendor Talk:  Esperanto Technologies ET-SoC for AI and ML W
 orkloads\n\nLee Flanagin\n\nTag: Architecture and Networks, Hardware Techn
 ologies\n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Nic
 k Brown (Edinburgh Parallel Computing Centre (EPCC); University of Edinbur
 gh, Scotland); John Davis (Openchip); Andy Gothard (Siemens); John Leidel 
 (Tactical Computing Laboratories LLC, Texas Tech University); and Michael 
 Wong (Codeplay Software Ltd, Khronos Group Inc)
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