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DTSTART:19700308T020000
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DTSTAMP:20260422T000711Z
LOCATION:503-504
DTSTART;TZID=America/Denver:20231113T170000
DTEND;TZID=America/Denver:20231113T173000
UID:submissions.supercomputing.org_SC23_sess447_ws_pmbsf123@linklings.com
SUMMARY:Modeling Data Locality of Sparse Matrix-Vector Multiplication on t
 he A64FX
DESCRIPTION:Sergej-Alexander Breiter (Ludwig-Maxmilians-Universität Münche
 n), James D. Trotter (Simula Research Laboratory), and Karl Fürlinger (Lud
 wig-Maxmilians-Universität München)\n\nOne of the novel features of the Fu
 jitsu A64FX CPU is the sector cache. This feature enables hardware-support
 ed partitioning of the L1 and L2 caches and allows the programmer control 
 of which partition is used to place data in. This paper performs an in-dep
 th study of how to apply the sector cache to a frequently used sparse matr
 ix-vector multiplication (SpMV) kernel. A performance model based on reuse
  analysis is used to better understand situations where the sector cache l
 eads to improved reuse and to predict the cache behavior. The model correc
 tly predicts the number of L2 cache misses within 2–3 % for sequential and
  parallel SpMV with 48 threads using a collection of 490 sparse matrices. 
 Further experiments show the effect of various sector cache configurations
  on performance. A median speedup of about 1.05× is achieved, whereas the 
 maximum speedup is about 1.6×.\n\nTag: Modeling and Simulation, Performanc
 e Measurement, Modeling, and Tools\n\nRegistration Category: Workshop Reg 
 Pass\n\nSession Chairs: Simon Hammond (National Nuclear Security Administr
 ation (NNSA)); Stephen Jarvis (University of Birmingham, UK); and Steven A
 . Wright (University of York, England)\n\n
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