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DTSTART:19700308T020000
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DTSTAMP:20260422T000711Z
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DTSTART;TZID=America/Denver:20231113T110000
DTEND;TZID=America/Denver:20231113T113000
UID:submissions.supercomputing.org_SC23_sess447_ws_pmbsf112@linklings.com
SUMMARY:Reducing Memory Requirements for the IPU Using Butterfly Factoriza
 tions
DESCRIPTION:SeyedKazem Shekofteh, Christian Alles, and Holger Fröning (Hei
 delberg University, Institute of Computer Engineering (ZITI))\n\nHigh Perf
 ormance Computing (HPC) benefits from different improvements during last d
 ecades, specially in terms of hardware platforms to provide more processin
 g power while maintaining the power consumption at a reasonable level.  Th
 e Intelligence Processing Unit (IPU) is a new type of massively parallel p
 rocessor, designed to speedup parallel computations with huge number of pr
 ocessing cores and on-chip memory components connected with high-speed fab
 rics.  IPUs mainly target machine learning applications, however, due to t
 he architectural differences between GPUs and IPUs, especially significant
 ly less memory capacity on an IPU, methods for reducing model size by spar
 sification have to be considered. Butterfly factorizations are well-known 
 replacements for fully-connected and convolutional layers.  We examine how
  butterfly structures can be implemented on an IPU and study their behavio
 r and performance compared to a GPU.\n\nTag: Modeling and Simulation, Perf
 ormance Measurement, Modeling, and Tools\n\nRegistration Category: Worksho
 p Reg Pass\n\nSession Chairs: Simon Hammond (National Nuclear Security Adm
 inistration (NNSA)); Stephen Jarvis (University of Birmingham, UK); and St
 even A. Wright (University of York, England)\n\n
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