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DTSTAMP:20260422T000712Z
LOCATION:503-504
DTSTART;TZID=America/Denver:20231113T093000
DTEND;TZID=America/Denver:20231113T100000
UID:submissions.supercomputing.org_SC23_sess447_ws_pmbsf107@linklings.com
SUMMARY:Comparative Evaluation of Bandwidth-Bound Applications on the Inte
 l Xeon CPU MAX Series
DESCRIPTION:István Z. Reguly (Pázmány Péter Catholic University, Hungary)\
 n\nWe explore the performance of Intel Xeon MAX CPU Series, representing t
 he most significant new variation upon the classical CPU architecture sinc
 e the Xeon Phi. Given a large on-package high-bandwidth memory, the bandwi
 dth-to-compute ratio has significantly shifted compared to other CPUs on t
 he market. Since a large fraction of HPC workloads are sensitive to the av
 ailable bandwidth, we explore how this architecture performs on a selectio
 n of HPC proxies and applications that are mostly sensitive to bandwidth, 
 and how it compares to the previous 3rd generation Xeon processors (Ice La
 ke) and an EPYC 7003 Series Processor with 3D V-Cache Technology. We explo
 re performance with different parallel implementations (MPI, MPI+OpenMP, M
 PI+SYCL), compiled with different compilers and flags, and executed with o
 r without hyperthreading. We show how performance bottlenecks are shifted 
 from bandwidth to communication latencies for some applications, and demon
 strate speedups compared to the previous generation between 2.0x-4.3x.\n\n
 Tag: Modeling and Simulation, Performance Measurement, Modeling, and Tools
 \n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Simon Hamm
 ond (National Nuclear Security Administration (NNSA)); Stephen Jarvis (Uni
 versity of Birmingham, UK); and Steven A. Wright (University of York, Engl
 and)\n\n
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