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UID:submissions.supercomputing.org_SC23_sess447@linklings.com
SUMMARY:PMBS23: The 14th International Workshop on Performance Modeling, B
 enchmarking, and Simulation of High-Performance Computer Systems
DESCRIPTION:Verifying Performance Guidelines for MPI Collectives at Scale\
 n\nMPI collective communication operations are crucial for high-performanc
 e computing, making the efficient implementation of collective algorithms 
 essential for optimal application performance. While most MPI libraries pr
 ovide several algorithms for a specific collective operation, each may wor
 k bette...\n\n\nSascha Hunold (Technical University of Vienna)\n----------
 -----------\nPower Analysis of NERSC Production Workloads\n\nPower has bec
 ome a key limiting factor in supercomputing.  Understanding the power sign
 atures of current production workloads is essential to address this limit 
 and continue to advance scientific computing at scale. This paper analyzes
  the power characteristics of NERSC production workloads at the s...\n\n\n
 Zhengji Zhao, Ermal Rrapaj, Sridutt Bhalachandra, Brian Austin, Hai Ah Nam
 , and Nicholas Wright (Lawrence Berkeley National Laboratory (LBNL))\n----
 -----------------\nEvaluating the Potential of Elastic Jobs in HPC Systems
 \n\nIt is generally assumed that elastic parallel applications, with the a
 bility to dynamically resize their process count, would provide numerous b
 enefits to High-Performance Computing (HPC) systems and applications.  Sup
 porting this capability, however, requires significant effort at several l
 ayers of...\n\n\nDavid Eberius, Md. Wasi-ur- Rahman, and David Ozog (Intel
  Corporation)\n---------------------\nA Performance Model for Estimating t
 he Cost of Scaling to Practical Quantum Advantage\n\nWe present a simple p
 erformance model to estimate the qubit-count and runtime associated with l
 arge-scale error-corrected quantum computations. Our estimates extrapolate
  current usage costs of quantum computers and show that computing the grou
 nd state of the 2D Hubbard model, which is widely believe...\n\n\nDaan Cam
 ps, Katherine Klymko, Brian Austin, and Nicholas J. Wright (Lawrence Berke
 ley National Laboratory (LBNL))\n---------------------\nAdaptive Stopping 
 Rule for Performance Measurements\n\nPerformance variability in complex co
 mputer systems is a major challenge for accurate benchmarking and performa
 nce characterization, especially for tightly-coupled large-scale high-perf
 ormance computing systems. Point summaries of performance may be both unin
 formative, if they do not capture the ful...\n\n\nViyom Mittal, Pedro Brue
 l, Dejan Milojicic, and Eitan Frachtenberg (Hewlett Packard Enterprise (HP
 E))\n---------------------\nRisk-Aware Scheduling Algorithms for Variable 
 Capacity Resources\n\nThis work focuses on the design of scheduling algori
 thms for independent jobs that are submitted to a platform whose resource 
 capacity varies over time. Jobs are submitted online and assigned on a tar
 get machine by  the scheduler, which is agnostic to the rate and amount of
  resource variation.  The ...\n\n\nLucas Perotin (ENS Lyon), Chaojie Zhang
  (Microsoft Research), Rajini Wijayawardana (University of Chicago), Anne 
 Benoit and Yves Robert (ENS Lyon), and Andrew Chien (University of Chicago
 )\n---------------------\nSPEChpc 2021 Benchmarks on Ice Lake and Sapphire
  Rapids Infiniband Clusters:  A Performance and Energy Case Study\n\nWe as
 sess fundamental performance, power, and energy characteristics of the SPE
 Chpc 2021 benchmark suite on two clusters based on Intel Ice Lake and Sapp
 hire Rapids CPUs using MPI only. We use memory bandwidth, data volume, and
  scalability metrics in order to categorize the benchmarks and pinpoint r.
 ..\n\n\nAyesha Afzal and Georg Hager (Friedrich-Alexander University, Erla
 ngen-Nuremberg; Erlangen National High Performance Computing Center) and G
 erhard Wellein (Friedrich-Alexander University, Erlangen-Nuremberg; Depart
 ment of Computer Science)\n---------------------\nReducing Memory Requirem
 ents for the IPU Using Butterfly Factorizations\n\nHigh Performance Comput
 ing (HPC) benefits from different improvements during last decades, specia
 lly in terms of hardware platforms to provide more processing power while 
 maintaining the power consumption at a reasonable level.  The Intelligence
  Processing Unit (IPU) is a new type of massively paral...\n\n\nSeyedKazem
  Shekofteh, Christian Alles, and Holger Fröning (Heidelberg University, In
 stitute of Computer Engineering (ZITI))\n---------------------\nPMBS23: Th
 e 14th International Workshop on Performance Modeling, Benchmarking, and S
 imulation of High-Performance Computer Systems\n\nThe PMBS23 workshop is c
 oncerned with the comparison of high-performance computing systems through
  performance modeling, benchmarking or through the use of tools such as si
 mulators. We are particularly interested in research which reports the abi
 lity to measure and make tradeoffs in software/hardwar...\n\n\nSteven Wrig
 ht (University of York), Simon Hammond (National Nuclear Security Administ
 ration (NNSA)), and Stephen Jarvis (University of Birmingham)\n-----------
 ----------\nPMBS23 – Afternoon Break\n---------------------\nLatency and B
 andwidth Microbenchmarks of US Department of Energy Systems in the June 20
 23 Top 500 List\n\nAs a rule, Top 500 class supercomputers are extensively
  benchmarked as part of their acceptance testing process. However, barring
  publicly posted LINPACK / HPCG results, most benchmark results are often 
 inaccessible outside the hosting institution. Moreover, these higher level
  benchmarks do not prov...\n\n\nChristopher M. Siefert, Carl Pearson, and 
 Stephen L. Olivier (Sandia National Laboratories); Andrey Prokopenko (Oak 
 Ridge National Laboratory (ORNL)); and Jonathan Hu and Timothy J. Fuller (
 Sandia National Laboratories)\n---------------------\nPMBS23 – Morning Bre
 ak\n---------------------\nHardware Specialization:  Estimating Monte Carl
 o Cross-Section Lookup Kernel Performance and Area\n\nHardware specializat
 ion is one of the promising directions in the post-Moore era.  It is imper
 ative to understand how hardware specialization paradigms can benefit HPC.
   An essential question revolves around estimating the theoretical perform
 ance of an optimally specialized architecture without requ...\n\n\nKazutom
 o Yoshii, John Tramm, and Bryce Allen (Argonne National Laboratory (ANL));
  Tomohiro Ueno and Kentaro Sano (RIKEN Center for Computational Science (R
 -CCS)); and Andrew Siegel and Pete Beckman (Argonne National Laboratory (A
 NL))\n---------------------\nPhysical Oscillator Model for Supercomputing\
 n\nA parallel program together with the parallel hardware it runs on is no
 t only a vehicle to solve numerical problems, it is also a complex system 
 with interesting dynamical behavior: resynchronization and desynchronizati
 on of parallel processes, propagating phases of idleness, and the peculiar
  effect...\n\n\nAyesha Afzal and Georg Hager (Friedrich-Alexander Universi
 ty, Erlangen-Nuremberg; Erlangen National High Performance Computing Cente
 r) and Gerhard Wellein (Friedrich-Alexander University, Erlangen-Nuremberg
 ; Department of Computer Science)\n---------------------\nPMBS23 – Welcome
 \n---------------------\nA Reinforcement Learning-Based Backfilling Strate
 gy for HPC Batch Jobs\n\nHPC systems employ a scheduling technique called 
 “backfilling”, wherein low-priority jobs are scheduled earlier to use the 
 available resources that are waiting for the pending high-priority jobs. B
 ackfilling relies on job runtime to calculate the start time of the ready-
 to-schedule jobs ...\n\n\nElliot Kolker-Hicks and Di Zhang (University of 
 North Carolina at Charlotte) and Dong Dai (University of North Carolina, C
 harlotte)\n---------------------\nPMBS23 – Lunch Break\n------------------
 ---\nComparative Evaluation of Bandwidth-Bound Applications on the Intel X
 eon CPU MAX Series\n\nWe explore the performance of Intel Xeon MAX CPU Ser
 ies, representing the most significant new variation upon the classical CP
 U architecture since the Xeon Phi. Given a large on-package high-bandwidth
  memory, the bandwidth-to-compute ratio has significantly shifted compared
  to other CPUs on the mark...\n\n\nIstván Z. Reguly (Pázmány Péter Catholi
 c University, Hungary)\n---------------------\nModeling Data Locality of S
 parse Matrix-Vector Multiplication on the A64FX\n\nOne of the novel featur
 es of the Fujitsu A64FX CPU is the sector cache. This feature enables hard
 ware-supported partitioning of the L1 and L2 caches and allows the program
 mer control of which partition is used to place data in. This paper perfor
 ms an in-depth study of how to apply the sector cache t...\n\n\nSergej-Ale
 xander Breiter (Ludwig-Maxmilians-Universität München), James D. Trotter (
 Simula Research Laboratory), and Karl Fürlinger (Ludwig-Maxmilians-Univers
 ität München)\n\nTag: Modeling and Simulation, Performance Measurement, Mo
 deling, and Tools\n\nRegistration Category: Workshop Reg Pass\n\nSession C
 hairs: Simon Hammond (National Nuclear Security Administration (NNSA)); St
 ephen Jarvis (University of Birmingham, UK); and Steven A. Wright (Univers
 ity of York, England)
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