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DTSTAMP:20260422T000712Z
LOCATION:603
DTSTART;TZID=America/Denver:20231113T092000
DTEND;TZID=America/Denver:20231113T094000
UID:submissions.supercomputing.org_SC23_sess446_ws_qcs129@linklings.com
SUMMARY:Prototype of a Batched Quantum Circuit Simulator for the Vector En
 gine
DESCRIPTION:Keichi Takahashi (Tohoku University); Toshio Mori (Osaka Unive
 rsity, RIKEN); and Hiroyuki Takizawa (Tohoku University)\n\nState-of-the-a
 rt quantum circuit simulators have mostly focused on scaling the number of
  qubits. However, we argue that studying current noisy quantum computers a
 nd variational quantum algorithms benefits from high-throughput simulation
  of intermediate-scale quantum circuits. We present the first implementati
 on and evaluation of a batched quantum simulator on the NEC Vector Engine 
 (VE), a vector processor with massive memory bandwidth ideal for memory-in
 tensive state vector simulation. To take advantage of the long-vector arch
 itecture of VE, we design a parallelization strategy and memory layout sui
 ted for batched state vector simulation. Our preliminary evaluation shows 
 that the performance of our simulator on VE Type 20B outperforms a dual-so
 cket CPU system by 12x. Furthermore, the performance of VE is identical to
  that of cuStateVec on A100 40 GB, matching the peak bandwidth of the two 
 processors. This suggests the latest VE with higher memory bandwidth is ex
 pected to outperform A100.\n\nTag: Quantum Computing, Software Engineering
 \n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Yuri Alexe
 ev (NVIDIA Corporation); Bert de Jong (Lawrence Berkeley National Laborato
 ry (LBNL)); Travis Humble (Oak Ridge National Laboratory (ORNL), Quantum S
 cience Centre); Dmitry Liakh (NVIDIA Corporation); Hausi Muller (Universit
 y of Victoria, British Columbia; IEEE Quantum Week); and Ojas Parekh (Sand
 ia National Laboratories)\n\n
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