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DTSTAMP:20260422T000713Z
LOCATION:507
DTSTART;TZID=America/Denver:20231113T112000
DTEND;TZID=America/Denver:20231113T114000
UID:submissions.supercomputing.org_SC23_sess444_ws_waccpd110@linklings.com
SUMMARY:Characterizing the Performance of Triangle Counting on Graphcore's
  IPU Architecture
DESCRIPTION:Reet Barik (Argonne National Laboratory (ANL), Washington Stat
 e University) and Siddhisanket Raskar, Murali Emani, and Venkatram Vishwan
 ath (Argonne National Laboratory (ANL))\n\nIn recent years, we have seen a
 n emergence of novel spatial architectures to accelerate domain-specific w
 orkloads like Machine Learning. There is a need to investigate their perfo
 rmance characteristics for traditional HPC workloads for their tighter int
 egration with current and future heterogeneous compute resources. In this 
 work, we implement, optimize and evaluate a parallel algorithm for Triangl
 e Counting for graphs in Bulk Synchronous Parallel (BSP) model for Graphco
 re’s IPU architecture as well as discuss lessons learned. This study demon
 strates IPU's competency in handling such irregular workloads by providing
  an average speedup of up to 5.3x over NVIDIA A100 GPU on real-world datas
 ets.\n\nTag: Accelerators, Artificial Intelligence/Machine Learning, Algor
 ithms, Applications, Compilers, Data Movement and Memory, Heterogeneous Co
 mputing, Modeling and Simulation, Performance Optimization, Programming Fr
 ameworks and System Software, Runtime Systems\n\nRegistration Category: Wo
 rkshop Reg Pass\n\nSession Chairs: Maciej Cytowski (Pawsey Supercomputing 
 Research Centre; Commonwealth Scientific and Industrial Research Organisat
 ion (CSIRO), Australia); Verónica G. Melesse Vergara (Oak Ridge National L
 aboratory (ORNL)); and Jose Manuel Monsalve Diaz (Advanced Micro Devices (
 AMD))\n\n
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