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DTSTART;TZID=America/Denver:20231113T141800
DTEND;TZID=America/Denver:20231113T142100
UID:submissions.supercomputing.org_SC23_sess442_ws_whpc108@linklings.com
SUMMARY:Accelerating the HPC I/O for Low Latency and High Throughput with 
 16-Nanometer FPGA-Based Hardware Accelerators
DESCRIPTION:Babar Khan (TU Darmstadt Germany)\n\nThe existing HPC I/O stac
 k struggles with the growing demands of HPC scientific workloads. To start
  with the latency bottleneck, there is a deeply layered kernel hierarchy t
 o translate HPC I/O requests to the actual storage operations. This layere
 d architecture adds a significant overhead along the entire I/O request pa
 th. Measurements have shown that it takes between 18,000 and 20,000 instru
 ctions to send and receive a single fundamental 4KB I/O request. Our novel
  hardware/software framework, named DeLiBA, aims to bridge this gap by fac
 ilitating the development of software components within the HPC I/O stack 
 in user space, rather than the kernel space, and leverages a proven 16 nan
 ometer (nm) FPGA framework to quickly deploy the FPGA-based HPC I/O accele
 rators. Our initial results achieve a 10% increase in throughput and demon
 strates up to 2.3 times the I/O operations per second compared to conventi
 onal methods.\n\nTag: State of the Practice\n\nRegistration Category: Work
 shop Reg Pass\n\nSession Chairs: Elsa J. Gonsiorowski (Lawrence Livermore 
 National Laboratory (LLNL)) and Mozhgan Kabiri chimeh (NVIDIA Corporation)
 \n\n
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