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TZOFFSETFROM:-0600
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DTSTART;TZID=America/Denver:20231112T111900
DTEND;TZID=America/Denver:20231112T113500
UID:submissions.supercomputing.org_SC23_sess421_ws_rsdha108@linklings.com
SUMMARY:Accelerator Integration in a Tile-Based SoC:  Lessons Learned with
  a Hardware Floating Point Compression Engine
DESCRIPTION:Xueyang Liu (Georgia Institute of Technology); Patricia Gonzal
 ez-Guerrero (Lawrence Berkeley National Laboratory (LBNL)); Ivy (Bo) Peng 
 (KTH Royal Institute of Technology, Sweden); Ronald Minnich (Samsung Corpo
 ration); and Maya Gokhale (Lawrence Livermore National Laboratory (LLNL))\
 n\nHeterogeneous Intellectual Property (IP) hardware acceleration engines 
 have emerged as a viable path forward to improving performance in the wani
 ng of Moore’s Law and Dennard scaling. In this study, we design, prototype
 , and evaluate the HPC-specialized ZHW floating point compression accelera
 tor as a resource on a System on Chip (SoC). Our full hardware/software im
 plementation and evaluation reveal inefficiencies at the system level that
  significantly throttle the potential speedup of the ZHW accelerator. By o
 ptimizing data movement between CPU, memory, and accelerator, 6.9X is poss
 ible compared to a RISC-V64 core, and 2.9X over a Mac M1 ARM core.\n\nTag:
  Accelerators, Edge Computing, Heterogeneous Computing\n\nRegistration Cat
 egory: Workshop Reg Pass\n\nSession Chairs: Ali Akoglu (University of Ariz
 ona), Mehmet E Belviranli (Colorado School of Mines), and Seyong Lee (Oak 
 Ridge National Laboratory (ORNL))\n\n
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