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DTSTART;TZID=America/Denver:20231115T143000
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UID:submissions.supercomputing.org_SC23_sess252_exforum118@linklings.com
SUMMARY:NVMe Over CXL (NVMe-oC): An Ultimate Optimization of Host-Device D
 ata Movement
DESCRIPTION:Bernard Shung and San Chang (Wolley, Inc)\n\nCompute Express L
 ink (CXL), introduced in 2019, manages the Host-Accelerator coherency and 
 the Host-Memory interface.  CXL fabric further enables the disaggregated m
 emory architecture.  Most of the CXL developments are on the memory interf
 ace and not on the storage interface.  In this paper, Wolley evaluates the
  impact of CXL to the storage interface.\n\nNVMe protocol moves the data i
 n a block form from a Device to a Host memory utilizing the PCIe as the tr
 ansport.  There are several attempts to minimize such Host-Device data mov
 ement which is an important factor of performance bottleneck and power con
 sumption.  One such effort is Computational Storage that moves the compute
  from the Host to the Device, and the Device only sends the computed resul
 t back to the Host at a much lower data rate.\n\nWolley proposes using NVM
 e over CXL (NVMeoC) to optimize the Host-Device data movement.  In most ap
 plications, the Host only accesses a small portion of the entire block dat
 a retrieved from the Device.  With NVMeoC, the Device keeps a CXL staging 
 area that is managed as a part of the Host memory.  Once the block data is
  moved to the CXL staging memory through NVMe operation, the actual Host-D
 evice data movement using CXL.mem is just a fraction of the total block da
 ta. Wolley will compare in details of the latency and the power consumptio
 n between the NVMe over PCIe and NVMe over CXL in several different of app
 lications.\n\nTag: Architecture and Networks, Data Movement and Memory, Ha
 rdware Technologies\n\nRegistration Category: Tech Program Reg Pass, Exhib
 its Reg Pass\n\nSession Chair: Ivanna Park (Internet2)\n\n
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