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DTSTART;TZID=America/Denver:20231112T133000
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UID:submissions.supercomputing.org_SC23_sess214_tut141@linklings.com
SUMMARY:Leveraging SmartNICs for HPC Applications
DESCRIPTION:Richard Graham (NVIDIA Corporation), Jeffrey Young (Georgia In
 stitute of Technology), Antonio Peña (Barcelona Supercomputing Center (BSC
 )), Richard Vuduc (Georgia Institute of Technology), and Yong Qin and Geof
 froy Vallee (NVIDIA Corporation)\n\nThe past few years have witnessed a su
 rge in the number of advanced network adapters, known as "SmartNICs", that
  offer additional functionalities beyond standard packet processing capabi
 lities. These devices often feature programmable lightweight processing co
 res, FPGAs, and even CPU- and GPU-based platforms capable of running separ
 ate operating systems. Though primarily aimed at data center operations, s
 uch as infrastructure management, packet filtering, and I/O acceleration, 
 SmartNICs are increasingly being explored for high-performance computing (
 HPC) application acceleration.\n\n\nThis tutorial offers an in-depth explo
 ration of the state-of-the-art for SmartNICs and the emerging software eco
 systems supporting them. Attendees will engage in hands-on exercises to be
 tter understand how to use SmartNICs for HPC application acceleration, inc
 luding MPI collective operation offloading, OpenMP offload, and algorithmi
 c modifications to maximize on-board processing power. Participants will h
 ave the opportunity to execute these exercises using cutting-edge SmartNIC
 s like NVIDIA's BlueField-3 Data Processing Unit (DPU). The tutorial prese
 nters will discuss additional techniques for optimizing applications to ha
 rness SmartNICs as communication accelerators in HPC systems.\n\nTag: Acce
 lerators, Applications\n\nRegistration Category: Tutorial Reg Pass\n\n
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